This invention relates generally to a system and method for managing the power consumption of an electronic device and in particular to a system and method for managing the power consumption of a computer system having one or more electrical components.
With modem electrical systems, it is often desirable to be able to conserve power and reduce the power consumption of the electrical systems. For example, it is desirable to be able to reduce the power consumption of a computer system. For a desktop system that is plugged into an AC outlet, the desirability of power consumption is important. However, for a laptop computer system or any other type of portable computer system that uses battery power or some other limited power source, the desirability of power conservation is critical. In particular, the conservation of power during the operation of the computer system while it is connected to a limited capacity power supply, such as a battery, is critical. The conservation of power leads to longer battery life, which is very desirable.
In general, the power being consumed by an electrical device is equal to P=CV2F wherein P is the total power, in watts, being consumed by the electrical device, C is the capacitance of the electrical device nodes, V is a voltage being used by the electrical device, and F is the switching frequency of the signal being applied to the electrical circuit. Thus, an electrical device that operates at a high frequency uses more power than the same device at a lower frequency since the transistors and logic gates in the device at the higher frequency will switch more often. With modem electrical devices, the voltage being used by the device (which used to be 5 volts, was 3.3 volts and will soon become 1.8 volts and lower) is somewhat unchangeable since one is typically required to use whatever voltage is currently being required by the semiconductor manufacturers. Therefore, to lower the power being consumed by the electrical device, one can decrease the node capacitance of the electrical device or one can decrease the clock frequency being applied to the electrical device. The capacitance of the electrical device may be reduced by stopping the operation of one or more portions of the electrical device which reduces the overall switching node capacitance of the device.
The conservation/management of power in a portable electronic device can be achieved by various mechanisms. For example, a portable electronic device typically has one or more different discrete electrical elements/components such as a processor, one or more different memory devices, one or more different electrical buses, one or more input/output interfaces and one or more different peripheral devices which are connected to the buses. The peripheral devices may include a display, such as a liquid crystal display (LCD), a cathode ray tube (CRT) or the like, a persistent storage device, such as a hard disk drive, a removable media storage unit, optical drive, zip drive or the like, one or more input devices, such as a keyboard or mouse and one or more output devices, such as a speaker or an output port. In general, to reduce the power consumption of the portable electronic device, static power management strategies and dynamic power management strategies may be employed. Using static power management techniques, different elements of the portable electronic device may be powered down in order to reduce the power consumption of the portable electronic device by reducing the total capacitance of the portable electronic device. For example, the display of a laptop computer or the display of a portable music device may be powered down during periods when there is no user activity (e.g., the user has not touched the keyboard or mouse for some predetermined period of time). As another example, the hard disk drive of a laptop computer may spin down and stop during the same user inactivity periods. Thus, during periods of inactivity, static power management helps to reduce the power consumption of the system. Using dynamic power management techniques, even during periods of usage, the power consumption of one or more elements of the computer system may be reduced by reducing the effective clock frequency applied to the elements of the computer system for some predetermined amount of time.
The problem and limitation with conventional static and dynamic power management techniques is that one must be able to rapidly return an electrical element to its fastest clock frequency when its clock frequency has been reduced or stopped, otherwise the performance of the portable electronic device may be impaired. In some conventional systems, the clock frequency applied to one or more elements of the computer system is reduced by reducing the speed (e.g., slowing down) of the well known phase locked loop (PLL) which generates the clock signals for the portable electronic device. Then, the speed of the PLL is increased when it is necessary to increase the clock speed of the electrical element. The problem with that approach is that it takes too long to restore the clock frequency and the performance of the portable electronic device is degraded. In particular, the mechanisms used to sense the need to restore the clock frequency and the time that it takes to communicate that restoration command to the PLL is long, and the time that it takes the PLL to restore its original clock frequency is even longer, such that the total cumulative delay to restore the original clock frequency becomes prohibitively long.
It is desirable to provide a different technique that does not suffer the same problems and limitations as conventional dynamic power management systems. It is also desirable to provide a power management system that incorporates both static and dynamic power management techniques. Thus, it is desirable to provide a power consumption system and method and it is to this end that the present invention is directed.